Multi-level system memory with near memory capable of storing compressed cache lines

A computing system, comprising:

• a plurality of CPU processing cores;
• a multi-level system memory comprising a near memory and a far memory;
• a memory controller, the memory controller coupled between the plurality of CPU processing cores and the multi-level system memory, the memory controller comprising a), b), c), d) below:
• a) tag array circuitry to identify a set of logical super lines to which an incoming read or write request for a cache line is to be directed;
• b) management logic circuitry for the set of logical super lines to associate the incoming write or read request with a particular cache line of the set of logical super lines;
• c) compression circuitry to compress the cache line if the request is a write request and decompression circuitry to decompress the cache line if the request is a read request;
• d) write circuitry to break down the cache line into smaller units and write the smaller units into the near memory if the request is a write request and read circuitry to read from the memory side cache smaller units that the cache line is stored as within the near memory if the request is a read request.

A method, comprising:

• receiving a read or write request for a cache line;
• directing the request to a set of logical super lines based on the cache line's system memory address;
• associating the request with a cache line of the set of logical super lines;
• if the request is a write request:
• compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache;
• if the request is a read request:
• reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.