Preemptive cache writeback with transaction support
AssigneeAdvanced Micro Devices, Inc.
InventorsDavid A. ROBERTS, Elliot H. MEDNICK
Life of this patent
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Abstract
A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.
Claims20
A method, comprising:
- transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle;
- preemptively writing back, during a second cycle, a cache line containing dirty data from the second cache to the first cache based on the unused bandwidth message;
- and
- writing over, in response to a cache miss to the second cache, the cache line in the second cache.
A processing system, comprising:
- a private cache associated with a processor core of a plurality of processor cores, the private cache comprising a private cache controller and a corresponding set of cache lines;
- and
- a shared cache shared by the plurality of processor cores, the shared cache comprising a shared cache controller and a shared set of cache lines, wherein the shared cache controller is configured to communicate an unused bandwidth message to the private cache controller in the private cache representing an unused bandwidth between the shared cache and the private cache during a first cycle.
A processor, comprising:
- a private cache associated with a processor core of a plurality of processor cores, the private cache comprising a private cache controller and a corresponding set of cache lines;
- and
- a shared cache shared by the plurality of processor cores, the shared cache comprising a shared cache controller and a shared set of cache lines, wherein the shared cache controller is configured to communicate an unused bandwidth message to the private cache controller in the private cache representing an unused bandwidth between the shared cache and the private cache during a first cycle.
Dependencies are inferred from the claim text.