Apparatus, system, integrated circuit die, and method to determine when to bypass a second level cache when evicting modified data from a first level cache

A system, comprising:

• a first level cache;
• a second level cache;
• a third level cache;
• a memory management unit to:
• process a first cache line in the first level cache having modified data for an address, wherein each cache line of cache lines in the first level cache stores data for one of a plurality of addresses stored in multiple cache lines of the second level cache;
• select a second cache line in the second level cache;
• determine a number of corresponding bits in the first cache line and the second cache line that are different;
• and
• write bits in the first cache line that are different from the corresponding bits in the second cache line to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.

An integrated circuit die in communication with a last level cache, comprising:

• a plurality of processing cores, each processing core including a first level cache and a memory management unit;
• and
• a second level cache,
• wherein the memory management unit in each processing core of the processing cores is to:
• process a first cache line in the first level cache, in the processing core having the memory management unit, having modified data for an address, wherein each cache line of cache lines in the first level cache stores data for one of a plurality of addresses stored in multiple cache lines of the second level cache;
• select a second cache line in the second level cache;
• determine a number of corresponding bits in the first cache line and the second cache line that are different;
• and
• write bits in the first cache line that are different from the corresponding bits in the second cache line to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.

A method for caching data in a hierarchy of caches, comprising:

• processing a first cache line in a first level cache having modified data for an address, wherein each cache line of cache lines in the first level cache stores data for one of a plurality of addresses stored in multiple cache lines of a second level cache;
• selecting a second cache line in the second level cache;
• determining a number of corresponding bits in the first cache line and the second cache line that are different;
• and
• writing bits in the first cache line that are different from the corresponding bits in the second cache line to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.