Registering clock driver controlled decision feedback equalizer training process
AssigneeIntel Corporation
InventorTonia G. MORRIS
Life of this patent
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Abstract
A method is described. The method includes receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit. The method also includes controlling the next testing sequence. The testing sequence includes sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit. The method includes sending results of the testing sequence to the memory controller. The results are to determine a value for the DFE tap coefficient.
Claims20
A driver circuit, comprising:
- a) an input to receive a control signal from a memory bus;
- b) redriver circuitry to redrive the control signal to multiple memory chips;
- c) a decision feedback equalizer (DFE) receiver circuit coupled between the input and the redriver circuitry, the DFE receiver circuit comprising a primary slicer circuit and a secondary slicer circuit;
- d) a training controller to control a training process to determine a tap coefficient value for said DFE performed by the driver circuit, said training controller to control a sweep of tap coefficient values during said training and control a sweep of a voltage of one of said slicers during said training, said control signal compared against the voltage by said one of said slicers to determine its logical vale.
A memory controller, comprising:
- a) an interface to a double data rate (DDR) memory bus;
- b) test pattern generation logic circuitry to generate test patterns to determine a coefficient tap value for a distributed feedback analyzer (DFE);
- c) a control circuit to perform a DFE coefficient tap training process for the DFE in which a driver circuit that is coupled to the memory controller through the interface includes the DFE and controls sweeps of the coefficient tap value and a voltage of a slicer that receives the test patterns during the DFE coefficient tap training process, the control circuit to determine range and/or increment information for the sweeps and send the information to the driver circuit.
A method performed by a driver circuit, comprising:
- receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit;
- controlling the testing sequence, the testing sequence comprising sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit;
- and,
- sending results of the testing sequence to the memory controller, the results to determine a value for the DFE tap coefficient.
Dependencies are inferred from the claim text.