Method to select flash memory blocks for refresh after read operations

A system, comprising:

• memory cells arranged in blocks;
• and
• a memory controller coupled to the memory cells for controlling program and read operations of the memory cells;
• wherein the memory controller is configured to:
• identify a plurality of error cells that have errors and determine a total number of error cells;
• determine a first error count e+ that represents a number of cell-errors in the direction of increasing cell-level and a second error count e− that represents a number of cell-errors in the direction of decreasing cell-levels;
• and
• perform a memory operation based on the first error count and the second error count.

A method of controlling a storage system, the storage system including a plurality of memory cells arranged in blocks and a memory controller coupled to the plurality of memory cells for controlling data write and read in the plurality of memory cells, the method comprising:

• selecting a block of memory cells, wherein each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages (PVs) from PV0 to PVN, where PV0<PV1< . . . <PVN, N being an integer;
• reading multiple memory cells in the block to determine a programmed data state of each memory cell;
• performing error correction decoding of the multiple memory cells to determine a corrected data state of each memory cell;
• for each memory cell, determining a read programmed voltage (PV-r) corresponding to the programmed data state determined by reading the memory cell, and determining a corrected programmed voltage (PV-c) corresponding to the corrected data state determined by the error correction decoding;
• identifying a plurality of error cells that have errors and a total number of error cells;
• determining a first error count that represents a total number of error cells that have a higher read programmed voltage (PV-r) than corrected programmed voltage (PV-c);
• determining a second error count that represents a total number of error cells that have a lower read programmed voltage (PV-r) than corrected programmed voltage (PV-c);
• and
• performing a memory operation based on the first error count and the second error count.