Parity bits location on i3c multilane bus

A method for data communication, comprising:

• configuring a plurality of devices coupled to a bus such that, in a first mode of operation, the plurality of devices exchange data in a signal transmitted on a first lane of the bus in accordance with timing provided by a clock signal transmitted on a second lane of the bus;
• determining availability of one or more additional lanes connecting two or more devices in the plurality of devices;
• and
• configuring the two or more devices to use the first lane and at least one of the additional lanes for data transmissions in a second mode of operation.

A processor-readable storage medium having one or more instructions which, when executed by at least one processor of a processing circuit, cause the processing circuit to:

• configure a plurality of devices coupled to a bus such that, in a first mode of operation, the plurality of devices exchange data in a signal transmitted on a first lane of the bus in accordance with timing provided by a clock signal transmitted on a second lane of the bus;
• determine availability of one or more additional lanes connecting two or more devices in the plurality of devices;
• and
• configure the two or more devices to use the first lane and at least one of the additional lanes for data transmissions in a second mode of operation.

A data communication apparatus comprising:

• means for configuring a plurality of devices coupled to a bus such that, in a first mode of operation, the plurality of devices exchange data in a signal transmitted on a first lane of the bus in accordance with timing provided by a clock signal transmitted on a second lane of the bus;
• means for determining availability of one or more additional lanes connecting two or more devices in the plurality of devices;
• and
• means for configuring the two or more devices to use the first lane and at least one of the additional lanes for data transmissions in a second mode of operation.