Methods and apparatus to facilitate field-programmable gate array support during runtime execution of computer readable instructions

A method comprising:

• compiling via a logic circuit, prior to runtime, a function written as high level source code into a first hardware bitstream kernel corresponding to the function and a second hardware bitstream kernel, different than the first hardware bitstream kernel, corresponding to the function;
• selecting, via a logic circuit, the first hardware bitstream kernel to be dispatched during runtime based on an attribute;
• dispatching, via a logic circuit, the first hardware bitstream kernel to a FPGA during runtime;
• and
• when an FPGA attribute does not satisfy a threshold during runtime, adjusting, via a logic circuit, the selection of the first hardware bitstream kernel to the second hardware bitstream kernel to be dispatched during runtime to execute the function.

A non-transitory computer readable storage medium comprising instructions which, when executed, cause a machine to at least:

• compile via a logic circuit, prior to runtime, a function block of code written as high level source code into a first hardware bitstream kernel corresponding to the function and a second hardware bitstream kernel, different from the first hardware bitstream kernel, corresponding to the function;
• select, via a logic circuit, the first hardware bitstream kernel to be dispatched during runtime based on an attribute;
• dispatch, via a logic circuit, the first hardware bitstream kernel to a FPGA during runtime;
• and
• when an FPGA attribute does not satisfy a threshold during runtime, adjust via a logic circuit, the selection of the first hardware bitstream kernel to the second hardware bitstream kernel to be dispatched during runtime to execute the function.