Method to coordinate system boot and reset flows and improve reliability, availability and serviceability (ras) among multiple chipsets

A method comprising:

• probing, by a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, the master chipset further connected to one or more non-master chipsets by a sideband messaging channel, a subset of the multiple interfaces to discover a topology of connected processors and non-master chipsets;
• and
• using, by the master chipset, the sideband messaging channel to coordinate a synchronized boot flow with the one or more non-master chipsets.

An apparatus comprising:

• a master chipset connected, using one or more standard interfaces, to a non-master chipset, at least one other non-master chipset, and at least one processor;
• the master chipset further connected to the non-master chipsets using a sideband messaging channel;
• wherein the master chipset is to use the sideband messaging channel to exchange messages with the non-master chipsets to implement a coordinated boot flow, a coordinated reset flow, and a coordinated power state transition flow.