Dynamic Reconfiguration of Multi-core Processor

A method for re-configuring a multi-core microprocessor having a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, each processing core configured to receive a disable instruction, the method comprising the disable instruction targeting any enabled one of the plurality of processing cores causes each of the non-targeted cores:

• getting interrupted and receiving reconfiguration information sent by the targeted core, going into a first sleep state, and staying in the first sleep state until the other cores go into the first sleep state;
• waking up after the other cores have gone into the first sleep state, going into a second sleep state, and staying in the second sleep state until the other cores go into the second sleep state;
• and
• waking up after the other cores have gone into the second sleep state and reading the configuration register, updated by the targeted core, to determine which of the plurality of processing cores is enabled or disabled;
• wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores.

A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

• computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising first program code for specifying a plurality of processing cores and second program code for specifying a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores;
• wherein a disable instruction targeting any enabled one of the plurality of processing cores causes each of the non-targeted cores to:
• get interrupted and receive reconfiguration information sent by the targeted core, go into a first sleep state, and stay in the first sleep state until the other cores go into the first sleep state;
• wake up after the other cores have gone into the first sleep state, go into a second sleep state, and stay in the second sleep state until the other cores go into the second sleep state;
• and
• wake up after the other cores have gone into the second sleep state and read the configuration register, updated by the targeted core, to determine which of the plurality of processing cores is enabled or disabled;
• wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores.