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US 2019/0095210 A1Published application
Instruction for determining histograms
AssigneeIntel Corporation
InventorShih Shigjong KUO
Life of this patent
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Abstract
A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
Claims22
A processor comprising:
- a decoder to decode a histogram instruction to perform histogram binning operations;
- a processor storage to store a first plurality of data elements to be processed by the histogram instruction;
- at least one packed data register to store a second plurality of data elements, each data element of the second plurality of data elements to store a count associated with a histogram bin;
- and
- execution circuitry to perform histogram binning operations responsive to the histogram instruction, the execution circuitry comprising:
- bin selection circuitry to select one of the second plurality of data elements responsive to a value of each of the first plurality of data elements, and
- bin update circuitry to increase the count in each of the second plurality of data elements selected by the bin selection circuitry.
4 more elements
A method comprising:
- decoding a histogram instruction to perform histogram binning operations into a decoded histogram instruction with a decoder of a processor;
- storing a first plurality of data elements to be processed by the histogram instruction in a processor storage of the processor;
- and
- executing the decoded histogram instruction to perform histogram binning operations with execution circuitry comprising:
- bin selection circuitry selecting one of a second plurality of data elements in at least one packed data register of the processor responsive to a value of each of the first plurality of data elements, each data element of the second plurality of data elements to store a count associated with a histogram bin, and
- bin update circuitry increasing the count in each of the second plurality of data elements selected by the bin selection circuitry.
3 more elements
A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
- decoding a histogram instruction to perform histogram binning operations into a decoded histogram instruction with a decoder of a processor;
- storing a first plurality of data elements to be processed by the histogram instruction in a processor storage of the processor;
- and
- executing the decoded histogram instruction to perform histogram binning operations with execution circuitry comprising:
- bin selection circuitry selecting one of a second plurality of data elements in at least one packed data register of the processor responsive to a value of each of the first plurality of data elements, each data element of the second plurality of data elements to store a count associated with a histogram bin, and
- bin update circuitry increasing the count in each of the second plurality of data elements selected by the bin selection circuitry.
3 more elements
A processor comprising:
- a decoder to decode a histogram instruction to perform histogram binning operations;
- a processor storage to store a first plurality of data elements to be processed by the histogram instruction;
- at least one packed data register to store a second plurality of data elements, each data element of the second plurality of data elements to store a count associated with a histogram bin;
- and
- execution circuitry to perform histogram binning operations responsive to the histogram instruction, the execution circuitry comprising:
- means to select one of the second plurality of data elements responsive to a value of each of the first plurality of data elements, and
- means to increase the count in each of the second plurality of data elements selected by the means to select one of the second plurality of data elements.
4 more elements
Dependencies are inferred from the claim text.