Processing device, arithmetic unit, and control method of processing device

An arithmetic unit performing an operation corresponding to an immediate instruction for instructing a calculation of a product of an immediate value and a constant and for instructing an operation of the product and data retained in a register file, the arithmetic unit comprising:

• a first arithmetic operation module configured to calculate the product of the immediate value and the constant;
• and
• a second arithmetic operation module configured to perform the operation of the product and the data retained in the register file,
• the first arithmetic operation module including
• a first shift operation unit configured to generate a first shifted value based on the first shift control information, by bit-shifting the immediate value received from the instruction decoder,
• a second shift operation unit configured to generate a second shifted value based on the second shift control information, the second shifted value being a value obtained by bit-shifting the immediate value, a value obtained by bit-shifting a complement of the immediate value, or “0”, and
• an add operation unit configured to calculate the product by performing an addition of the first shifted value and the second shifted value.

A method of controlling a processing device including an instruction decoder configured to generate instruction information by decoding an instruction, an arithmetic unit configured to perform an arithmetic operation based on the instruction information, and a register file configured to retain data used for the arithmetic operation, the method comprising:

• generating, in a case in which the instruction decoder has decoded an immediate instruction for instructing a calculation of a product of an immediate value and a constant and for instructing an operation of the product and data retained in the register file, a first shift control information and a second shift control information by the instruction decoder based on the constant;
• generating, by the arithmetic unit, a first shifted value based on the first shift control information, by bit-shifting the immediate value received from the instruction decoder;
• generating, by the arithmetic unit, a second shifted value based on the second shift control information, the second shifted value being a value obtained by bit-shifting the immediate value, a value obtained by bit-shifting a complement of the immediate value, or “0”;
• calculating, by the arithmetic unit, the product by performing an addition of the first shifted value and the second shifted value;
• and
• performing, by the arithmetic unit, the operation of the product and the data retained in the register file.