Memory system and operating method thereof
AssigneeSK hynix Inc.
InventorsIn JUNG, Soo Nyun KIM
Life of this patent
Estimating the term…
Abstract
A memory system includes: a flash translation layer block suitable for receiving data from a host and converting a logic address into a physical address to store address information, during a write operation; a first buffer unit suitable for sequentially receiving the data from the flash translation layer; and a second buffer unit suitable for randomly receiving the data from the flash translation layer, wherein the flash translation layer block outputs data to only one of the first and second buffer units in a fast write mode during the write operation, and updates mapping information on the data stored in the one of the first and second buffer units after the fast write mode is terminated.
Claims21
1-3. (canceled)
A device comprising:
- a semiconductor memory;
- and
- a memory controller having a buffer block including a random buffer unit and a sequential buffer unit, the memory controller programmable to switch between a normal write mode that uses both the random buffer unit and the sequential buffer unit for writing to the semiconductor memory, and a fast write mode that uses the random buffer unit and not the sequential buffer unit for writing to the semiconductor memory,
- wherein in the normal write mode, the memory controller is configured to compare an address of data stored in the sequential buffer unit and an address of data stored in the random buffer unit, perform a duplicated address invalidation operation to invalidate the data in the random buffer unit having the same address and update mapping information for the data stored in the buffer block, and write to the semiconductor memory, and
- wherein in the fast write mode, the memory controller is configured to write to the semiconductor memory without performing the duplicated address invalidation operation.
A method comprising:
- performing a write operation to a semiconductor memory in a fast write mode that uses a random buffer unit of a buffer block but not a sequential buffer unit of the buffer block, wherein the semiconductor memory is operable in the fast write mode without a duplicated address invalidation operation;
- switching from the fast write mode to a normal write mode that uses both the random buffer unit and the sequential buffer unit of the buffer block;
- and
- subsequent to switching to the normal write mode:
- comparing an address of data stored in the sequential buffer unit and an address of data stored in the random buffer unit;
- performing the duplicated address invalidation operation to invalidate the data having the same address in the random buffer unit;
- and
- updating mapping information for the data stored in the buffer block.
A device comprising:
- a semiconductor memory;
- and
- a memory controller having a buffer block including a first buffer unit and a second buffer unit, the memory controller programmable to switch between a first write mode that uses both the first and second buffer units for writing to the semiconductor memory, and a second write mode that uses the first buffer unit and not the second buffer unit for writing to the semiconductor memory,
- wherein in the first write mode, the memory controller is configured to compare an address of data stored in the first buffer unit and an address of data stored in the second buffer unit, perform a duplicated address invalidation operation to invalidate the data in the first buffer unit having the same address and update mapping information for the data stored in the buffer block, and write to the semiconductor memory, and
- wherein in the second write mode, the memory controller is configured to write to the semiconductor memory without performing the duplicated address invalidation operation.
Dependencies are inferred from the claim text.