Data transfers with adaptively adjusted polling times
AssigneeSeagate Technology LLC
InventorsTimothy Canepa, Stephen Hanna
Life of this patent
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Abstract
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.
Claims20
An apparatus comprising:
- a memory module comprising a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM;
- a statistics table configured to store accumulated statistics of a history of data transfer command wait periods associated with a subset of the memory cells of the NVM;
- and
- a controller circuit configured to issue data transfer commands at a first delay rate to the MME circuit, each command including an address within a range of addresses of the subset of the memory cells and a data transfer action to be taken by the MME circuit in relation to the included address, the controller circuit further configured to analyze the stored statistics of the statistics table and adjust the first delay rate to a second delay rate based on the analyzing, the controller circuit further configured to issue further data transfer commands at the second delay rate to the MME circuit in relation to the subset of the memory cells.
A method comprising:
- issuing data transfer commands at a first delay rate to a memory module electronics (MME) circuit, each command including an address within a range of addresses of a subset of the memory cells of a solid-state non-volatile memory (NVM) and a data transfer action to be taken by the MME circuit in relation to the included address;
- accumulating statistics of a history of data transfer command wait periods associated with the subset;
- storing the accumulated history statistics as a statistics table in a data structure in local memory;
- analyzing the stored statistics;
- adjusting the first delay rate to a second delay rate based on the analyzing;
- and
- issuing further data transfer commands at the second delay rate to the MME circuit in relation to the subset of the memory cells.
Dependencies are inferred from the claim text.