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US 2019/0095098 A1Published application
Semiconductor memory device relating to the determination of a majority or minority level and semiconductor system including the same
AssigneeSK hynix Inc.
InventorJae Woong YUN
Life of this patent
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Abstract
A semiconductor memory device may include a data-determining circuit and a memory cell array. The data-determining circuit may receive data to determine a majority level of data among the received data. The data-determining circuit may provide data bus inversion information to invert data of an address including a minority level of data. The memory cell array may store the data bus inversion information through a redundant bit line.
Claims13
A semiconductor memory device comprising:
- a data-determining circuit configured to receive data and determine a majority level of data among the received data, and provide data bus inversion information for inverting data of an address having a minority level of data;
- and
- a storing circuit configured to store the data bus inversion information through a redundant data line.
A semiconductor memory device comprising:
- a global input and output (input/output) (GIO) driving circuit configured to receive data through a GIO line;
- a data-determining circuit configured to determine majority and minority levels of the data inputted through the GIO line and to provide the GIO driving circuit with data bus inversion information for inverting a minority level of data;
- a local input/output (LIO) driving circuit configured to receive and drive the data and the data bus inversion information outputted from the GIO driving circuit;
- and
- a memory cell array including a plurality of memory cells and a redundant memory cell configured to store the data and the data bus inversion information from the LIO driving circuit.
2 more elements
A semiconductor system comprising:
- a controller configured to output a write command and a read command for inputting and outputting data;
- and
- a semiconductor memory device including data-determining circuit configured to receive the data and determine a majority level of data among the received data, and provide data bus inversion information for inverting data of an address having a minority level of data, and a redundant memory cell configured to store the data bus inversion information.
Dependencies are inferred from the claim text.