Power-aware scan partitioning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAnkita Patidar, Sandeep Kumar Goel, Yun-Han Lee
Life of this patent
Estimating the term…
Abstract
Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
Claims20
A method of scan partitioning a circuit, the method comprising:
- calculating a power score for each of a plurality of circuit cells within a circuit design based on one or more physical cell parameters of the plurality of circuit cells used in the circuit design;
- for each of the plurality of circuit cells, assigning the circuit cell to a scan group from among a plurality of scan groups according to the power score for the circuit cell and a total power score for each scan group;
- and
- forming a plurality of scan chains, wherein each of the plurality of scan chains is formed from the circuit cells in a corresponding scan group of the plurality of scan groups based at least in part on placement data within the circuit design for each of the circuit cells included in the corresponding scan group.
A method of scan partitioning a circuit, the method comprising:
- calculating a power score for each of a plurality of circuit cells within a circuit design based on one or more physical cell parameters of the plurality of circuit cells used in the circuit design and independently of a test pattern to be applied to the circuit;
- for each of the plurality of circuit cells, assigning the circuit cell to a scan group from among a plurality of scan groups based on the power score for the circuit cell and a total power score for each scan group;
- and
- for each scan group, forming a scan chain for each of the circuit cells included in the scan group.
A system for partitioning circuit cells of a circuit design into scan groups useable to form scan chains in the circuit design, the system comprising:
- a programmable circuit;
- a memory operatively connected to the programmable circuit, the memory storing instructions which, when executed by the programmable circuit, cause the system to perform:
- calculating a power score for each of a plurality of circuit cells within a circuit design based on one or more physical cell parameters of the plurality of circuit cells used in the circuit design;
- sorting the plurality circuit cells according to the power score;
- defining a plurality of scan groups;
- selecting a highest unassigned circuit cell of the plurality of circuit cells;
- assigning the highest unassigned circuit cell to a scan group of the plurality of scan groups having a lowest aggregate power score.
Dependencies are inferred from the claim text.