Ensuring completeness of interface signal checking in functional verification

A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

• performing, a static source code analysis of a verification software source code, resulting in a list of interface signals to be verified in a checker control flow database;
• adding an attribute value and code to an interface signal variable to the verification software source code, resulting in instrumented verification software source code;
• executing the instrumented verification software source code against a chip design, resulting in a trace file;
• determining, from the trace file, occurrences of accesses to the interface signal variable;
• and
• matching the occurrences with the checker control flow database, resulting in a list of interface signal variables that have not been checked by executing the verification software source code.

A computer implemented method comprising:

• performing, by a computer system, a static source code analysis of a verification software source code, resulting in a list of interface signals to be verified in a checker control flow database;
• adding a color and a code to an interface signal variable to the verification software source code, resulting in an instrumented verification software source code;
• executing the instrumented verification software source code, against a chip design, resulting in a trace file;
• determining, from the trace file, occurrences of accesses to the interface signal variable;
• and
• matching the occurrences with the checker control flow database, resulting in a list of interface signal variables that have not been checked by executing the verification software source code.