Output resistance testing integrated circuit

An integrated circuit (IC) comprising:

• a first transistor having a first dopant type, the first transistor comprising:
• a first terminal configured to receive a current;
• a second terminal connected to a node;
• and
• a first gate;
• a second transistor having a second dopant type opposite to the first dopant type, the second transistor comprising:
• a first terminal connected to a device under test (DUT);
• a second terminal connected to the node;
• and
• a second gate;
• and
• a first programmable e-fuse coupled between the node and one of the first gate or the second gate,
• wherein the first gate is capable of receiving a first voltage from a first voltage source simultaneously with the second gate receiving a second voltage from a second voltage source, the first voltage being different from the second voltage.

An integrated circuit (IC) comprising:

• a first transistor having a first dopant type, the first transistor comprising:
• a first terminal configured to receive a current;
• a second terminal connected to a node;
• and
• a first gate;
• a second transistor having a second dopant type opposite to the first dopant type, the second transistor comprising:
• a first terminal connected to a device under test (DUT);
• a second terminal connected to the node;
• and
• a second gate;
• and
• a first programmable e-fuse coupled between the first terminal of the second transistor and a reference voltage connection,
• wherein each one of the first gate, the node, or the second gate is capable of receiving a first voltage from a first voltage source simultaneously with another one of the first gate, the node, or the second gate receiving a second voltage from a second voltage source, the first voltage being different from the second voltage.