Clock signal inspection device, plant monitoring controller, and method for diagnosing clock signal inspection device

A clock signal inspection device comprising:

• a first clock signal inspection circuit including
• a first counter to which a first clock signal is inputted and which counts the first clock signal for a first time,
• a first comparison counter to which a second clock signal having the same frequency as that of the first clock signal is inputted and which counts the second clock signal and outputs a count value of the second clock signal in response to an output signal from the first counter,
• a first comparator which compares an expected value expected to be obtained by the first comparison counter counting the second clock signal for the first time, with the count value outputted from the first comparison counter, and outputs an error signal if there is an error therebetween, and
• a first output circuit which outputs the error signal to the outside in response to the output signal from the first counter when the error signal is inputted from the first comparator;
• and
• a second clock signal inspection circuit including
• a second counter to which the second clock signal is inputted and which counts the second clock signal for the first time,
• a second comparison counter to which the first clock signal is inputted and which counts the first clock signal and outputs a count value of the first clock signal in response to an output signal from the second counter,
• a second comparator which compares an expected value expected to be obtained by the second comparison counter counting the first clock signal for the first time, with the count value outputted from the second comparison counter, and outputs an error signal if there is an error therebetween, and
• a second output circuit which outputs the error signal to the outside in response to the output signal from the second counter when the error signal is inputted from the second comparator, wherein
• in the first clock signal inspection circuit,
• a time for which count is performed by the first counter is changed from the first time to a second time,
• the first comparator compares the count value of the second clock signal outputted from the first comparison counter in response to the output signal from the first counter, with the expected value expected to be obtained by the first comparison counter counting the second clock signal for the first time, and outputs the error signal, and
• then, the time for which count is performed by the first counter is changed from the second time to the first time, the first comparator compares the expected value expected to be obtained by the first comparison counter counting the second clock signal for the first time, with the count value of the second clock signal outputted from the first comparison counter, and soundness of the first clock signal inspection circuit is determined.