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US 2019/0068200 A1Published application
Digital phase locked loop frequency estimation
AssigneeIntel IP Corporation
InventorsElan Banin, Roy Amel, Ran Shimon, Ashoke Ravi, Nati Dinur
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Abstract
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
Claims23
A Digital Phase Locked Loop (DPLL), comprising:
- a Time-to-Digital Converter (TDC) configured to generate quantized phase values of a controlled oscillator signal;
- and
- a frequency estimation circuit configured to receive the quantized phase values, determine a wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
A method of operating a Digital Phase Locked Loop (DPLL), comprising:
- generating, by a Time-to-Digital Converter (TDC), quantized phase values of a controlled oscillator signal;
- determining, by a frequency estimation circuit, a wraparound phase of the quantized phase values;
- and
- least-squares estimating, by the frequency estimation circuit, a frequency based on the quantized phase values and the wraparound phase.
1 more element
Dependencies are inferred from the claim text.