# US 2019/0065759 A1 · Method for protecting data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0065759 A1 - Document ID: US20190065759A1 - Status: Published application - Kind: A1 - Application number: 16/108,653 - Filed: 2018-08-22 - Published: 2019-02-28 - Earliest claimed: 2017-08-24 - Assignees: Skeyecode - Applicants: Skeyecode - Inventors: Guillaume Pitel - Web page: https://patentgrep.com/patent/US20190065759A1 ## CPC - G06F 21/602: {Providing cryptographic facilities or services} - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) - H04L 9/00: {Cryptographic mechanisms or cryptographic} arrangements for secret or secure communications; Network security protocols - H04L 9/0618: {Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation} - H04L 9/0656: {Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher} - H04L 9/085: {Secret sharing or secret splitting, e.g. threshold schemes} - H04L 2209/16: Obfuscation or hiding, e.g. involving white box - H04L 2209/34: Encoding or coding, e.g. Huffman coding or error correction - H04L 2209/46: Secure multiparty computation, e.g. millionaire problem - H04L 2209/50: Oblivious transfer - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A method for encoding can include generating a data structure defining a Boolean circuit including a memory storing original data, inputs and outputs, logic gates, and wires interconnecting the inputs, the logic gates and the outputs, the memory including, for each bit of the original data, a memory cell including a logic gate performing a logic operation depending on a value of the bit, the Boolean circuit configured to receive input data for selecting and reading a memory cell, and to provide a binary data of a bit read in the selected memory cell and address data of the bit in the original data. Generating the data structure including: generating a valid data for each binary state of each wires of the Boolean circuit, and computing truth table values of the logic gates as a function of the valid input and output data, and a logical operation of the logic gate. ## Claims ### Claim 1 A method for encoding data comprising: generating a data structure defining a Boolean circuit including a memory storing original data, circuit inputs, circuit outputs, logic gates, and wires interconnecting the circuit inputs, the logic gates and the circuit outputs, the memory including, for each bit of the original data, a memory cell including a logic gate performing a logic operation depending on a value of the bit, the Boolean circuit being configured to receive input data for selecting and reading a memory cell in the memory, and to provide a binary data defining a value of a bit read in the selected memory cell and address data defining a position of the bit in the original data, the generating the data structure including: generating a valid data representing each binary state of each of the wires of the Boolean circuit, and computing, for each logic gate of the Boolean circuit, truth table values as a function of the valid data of the wires connected to the inputs of the logic gate, the valid data of the wire connected to the output of the logic gate and the logic operation performed by the logic gate. ### Claim 2 (canceled) ### Claim 3 (depends on 1) The method of claim 1, wherein each bit of the original data is computed from binary data stored in several of the memory cells. ### Claim 4 (depends on 1) The method of claim 1, wherein each of the memory cells of the memory of the Boolean circuit includes a logic gate having an input inverted or not, depending on the bit value stored by the memory cell. ### Claim 5 (depends on 1) The method of claim 1, wherein the Boolean circuit includes an address converting circuit configured to provide the address data of the bit as a function of circuit inputs provided to the Boolean circuit. ### Claim 6 (depends on 1) The method of claim 1, wherein the Boolean circuit is configured to select and read a plurality of memory cells simultaneously, and to provide binary data defining values of bits read in the selected plurality of memory cells and one address data. ### Claim 7 (depends on 1) The method of claim 1, wherein the circuit inputs include: selection signal inputs, each memory cell being connected to a single selection signal input, or address signals inputs, the Boolean circuit including an address decoding circuit providing selection signals as a function of signals applied to the address signals inputs, each memory cell receiving a single selection signal. ### Claim 8 (depends on 1) The method of claim 1, wherein the Boolean circuit includes an interconnection matrix randomly defined, the interconnection matrix connecting at least one of: read signal inputs of the Boolean circuit to memory cells of the Boolean circuit such that bit values stored in the memory are randomly distributed in the memory, a number of read signal inputs being randomly defined; or two gate layers of the Boolean circuit. ### Claim 9 (depends on 1) The method of claim 1, further comprising applying a computation to the data and to the address data, provided by one execution of the Boolean circuit, to obtain a bit value of the original data and the position of the bit value in the original data. ### Claim 10 (depends on 1) The method of claim 1, wherein computing output values of each logic gate of the Boolean circuit involves a secret key. ### Claim 11 A computing device for encoding data, the computing device being configured to: generate a data structure defining a Boolean circuit including a memory storing original data, circuit inputs, circuit outputs, logic gates, and wires interconnecting the circuit inputs, the logic gates and the circuit outputs, the memory including for each bit of the original data, a memory cell having a logic gate performing a logic operation depending on a value of the bit, the Boolean circuit being configured to receive input data for selecting and reading a memory cell in the memory, and to provide a binary data defining a value of a bit read in the selected memory cell and address data defining a position of the bit in the original data, the generation of the data structure including: generating a valid data representing each binary state of each of the wires of the Boolean circuit, and computing, for each logic gate of the Boolean circuit, truth table values as a function of the valid data of the wires connected to the inputs of the logic gate, the valid data of the wire connected to the output of the logic gate and the logic operation performed by the logic gate. ### Claim 12 (depends on 11) The computing device of claim 11, wherein each bit of the original data is computed from binary data stored in a plurality of the memory cells. ### Claim 13 (canceled) ### Claim 14 (canceled) ### Claim 15 A computer program product loadable into a computer memory and including code portions which, when executed by a computer, cause the computer to: generate a data structure defining a Boolean circuit including a memory storing original data, circuit inputs, circuit outputs, logic gates, and wires interconnecting the circuit inputs, the logic gates and the circuit outputs, the memory including, for each bit of the original data, a memory cell including a logic gate performing a logic operation depending on a value of the bit, the Boolean circuit being configured to receive input data for selecting and reading a memory cell in the memory, and to provide a binary data defining a value of a bit read in the selected memory cell and address data defining a position of the bit in the original data, the generating the data structure including: generating a valid data representing each binary state of each of the wires of the Boolean circuit, and computing, for each logic gate of the Boolean circuit, truth table values as a function of the valid data of the wires connected to the inputs of the logic gate, the valid data of the wire connected to the output of the logic gate and the logic operation performed by the logic gate. ### Claim 16 (depends on 11) The computing device of claim 11, wherein each of the memory cells of the memory of the Boolean circuit includes a logic gate having an input inverted or not, depending on the bit value stored by the memory cell. ### Claim 17 (depends on 11) The computing device of claim 11, wherein the Boolean circuit includes an address converting circuit configured to provide the address data of the bit as a function of circuit inputs provided to the Boolean circuit. ### Claim 18 (depends on 11) The computing device of claim 11, wherein the Boolean circuit is configured to select and read a plurality of memory cells simultaneously, and to provide binary data defining values of bits read in the selected plurality of memory cells and one address data. ### Claim 19 (depends on 11) The computing device of claim 11, wherein the circuit inputs include: selection signal inputs, each memory cell being connected to a single selection signal input, or address signals inputs, the Boolean circuit including an address decoding circuit providing selection signals as a function of signals applied to the address signals inputs, each memory cell receiving a single selection signal. ### Claim 20 (depends on 11) The computing device of claim 11, wherein the Boolean circuit includes an interconnection matrix randomly defined, the interconnection matrix connecting at least one of: read signal inputs of the Boolean circuit to memory cells of the Boolean circuit such that bit values stored in the memory are randomly distributed in the memory, a number of read signal inputs being randomly defined; or two gate layers of the Boolean circuit. ### Claim 21 (depends on 11) The computing device of claim 11, configured to apply a computation to the data and to the address data, provided by one execution of the Boolean circuit, to obtain a bit value of the original data and the position of the bit value in the original data. ### Claim 22 (depends on 11) The computing device of claim 11, wherein output values of each logic gate of the Boolean circuit are computed using a secret key.