Multi-port puf circuit based on mosfet current division deviations

A MULTI-PORT PUF CIRCUIT BASED ON MOSFET CURRENT DIVISION DEVIATIONS, CHARACTERIZED IN THAT COMPRISES:

• a reference source, comprising a 1st voltage output terminal, a 2nd voltage output terminal, a 3rd voltage output terminal and a current output terminal;
• a row decoder, comprising a control terminal, 128 input terminals and 7 output terminals;
• a column decoder, comprising a control terminal, 2 input terminals and 4 output terminals
• a timing controller, comprising a 1st output terminal and a 2nd output terminal;
• 32 PUF arrays, comprises a 512 PUF cells, an arbiter, a 1st inverter, a 2nd inverter, a 3rd inverter, a 4th inverter and 8 transmission gates, wherein each transmission gate is provided with a 1st control terminal, a 2nd control terminal, an input terminal and an output terminal;
• wherein the 8 transmission gates are a 1st transmission gate, a 2nd transmission gate, a 3rd transmission gate, a 4th transmission gate, a 5th transmission gate, a 6th transmission gate, a 7th transmission gate and an 8th transmission gate;
• wherein the arbiter is configured with a 1st input terminal, a 2nd input terminal, a 1st bias terminal, a 2nd bias terminal and an output terminal;
• wherein each of the PUF cell is comprises a control voltage input terminal, a control current input terminal, a selective signal input terminal, a 1st output terminal and a 2nd output terminal;
• wherein the 512 PUF cells are arranged in 128 rows and 4 columns and the control voltage input terminals of the 512 PUF cells are coupled;
• wherein a connecting terminal is a 1st control voltage input terminal of the corresponding PUF array, the control current input terminals of the 512 PUF cells are coupled, the connecting terminal is the control current input terminal of the corresponding PUF array,
• wherein the selective signal input terminals of the PUF cells in the mth row are coupled, the connecting terminal is the mth row selective signal input terminal of the corresponding PUF array, and m=1, 2, . . . , 128,
• wherein the 1st output terminals of the PUF cells in a 1st column are connected to an input terminal of the 1st transmission gate, the 2nd output terminals of the PUF cells in the 1st column are coupled to an input terminal of the 2nd transmission gate, the 1st output terminals of the PUF cells in the 2nd column are coupled to an input terminal of the 3rd transmission gate, the 2nd output terminals of the PUF cells in the 2nd column are coupled to an input terminal of the 4th transmission gate, the 1st output terminals of the PUF cells in the 3rd column are coupled to an input terminal of the 5th transmission gate, the 2nd output terminals of the PUF cells in the 3rd column are coupled to the input terminal of the 6th transmission gate, the 1st output terminals of the PUF cells in the 4th column are coupled to an input terminal of the 7th transmission gate, and the 2nd output terminals of the PUF cells in the 4th column are connected to an input terminal of the 8th transmission gate;
• wherein the 1st control terminal of the 1st transmission gate and the 1st control terminal of the 2nd transmission gate are connected to the input terminal of the 1st inverter, the connecting terminal is the 1st column selective signal input terminal of the corresponding PUF array,
• wherein the 2nd control terminal of the 1st transmission gate and the 2nd control terminal of the 2nd transmission gate are coupled to an output terminal of the 1st inverter, the 1st control terminal of the 3rd transmission gate and a 1st control terminal of the 4th transmission gate are coupled to an input terminal of the 2nd inverter, the connecting terminal is the 2nd column selective signal input terminal of the corresponding PUF array,
• wherein the 2nd control terminal of the 3rd transmission gate and the 2nd control terminal of the 4th transmission gate are coupled to an output terminal of the 2nd inverter, the 1st control terminal of the 5th transmission gate and the 1st control terminal of the 6th transmission gate are connected to the input terminal of the 3rd inverter, the connecting terminal is the 3rd column selective signal input terminal of the corresponding PUF array,
• wherein the 2nd control terminal of the 5th transmission gate and the 2nd control terminal of the 6th transmission gate are coupled to an output terminal of the 3rd inverter;
• the 1st control terminal of the 7th transmission gate and the 1st control terminal of the 8th transmission gate are coupled to an input terminal of the 4th inverter, the connecting terminal is the 4th column selective signal input terminal of the corresponding PUF array,
• wherein the 2nd control terminal of the 7th transmission gate and the 2nd control terminal of the 8th transmission gate are coupled to an output terminal of the 4th inverter;
• wherein an output terminal of the 1st transmission gate, an output terminal of the 3rd transmission gate, an output terminal of the 5th transmission gate and an output terminal of the 7th transmission gate are coupled to a 1st input terminal of the arbiter;
• an output terminal of the 2nd transmission gate, an output terminal of the 4th transmission gate, an output terminal of the 6th transmission gate and an output terminal of the 8th transmission gate are coupled to a 2nd input terminal of the arbiter;
• wherein the 1st bias terminal of the arbiter is a 2nd control voltage input terminal of the corresponding PUF array, and a 2nd bias terminal of the arbiter is a 3rd control voltage input terminal of the corresponding PUF array,
• wherein the 1st voltage output terminal of the reference source is coupled to the 1st control voltage input terminals of the PUF arrays, the 2nd voltage output terminal of the reference source is coupled to the 2nd control voltage input terminals of the 32 PUF arrays, the 3rd voltage output terminal of the reference source is coupled to a 3rd control voltage input terminals of the 32 PUF arrays, and the current output terminal of the reference source is coupled to a control current input terminal of the 32 PUF arrays,
• wherein a mth output terminal of the row decoder is coupled to a mth row selective signal input terminals of the 32 PUF arrays, a jth output terminal of the column decoder is coupled to the jth column selective signal input terminals of the 32 PUF arrays, and j=1, 2, 3, 4;
• wherein a 1st output terminal of the timing controller is coupled to a control terminal of the row decoder, and a 2nd output terminal of the timing controller is coupled to a control terminal of the column decoder.