US 2019/0058573 A1 · READ-WRITE DATA TRANSLATION TECHNIQUE OF ASYNCHRONOUS CLOCK DOMAINS

Abstract

An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.

Claims20

Dependent claims

A transmitting circuitry, comprising:

transmitter-edge-detect (TED) circuitry configured to compare a first clocking signal associated with a digital input signal and a second clocking signal of a first clock domain;
and
transmitter-cross-domain (TCD) circuitry configured to:
re-time the digital input signal in accordance with a falling edge of the second clocking signal when the first clocking signal is lagging the second clocking signal, and
re-time the digital input signal in accordance with a rising edge of the second clocking signal when the first clocking signal is leading the second clocking signal.

2 more elements

A method for transmitting a digital signal between a first clock domain and a second clock domain, the method comprising:

comparing, by a first circuit of the first clock domain, a first clocking signal associated with the digital input signal and a second clocking signal associated with the first clock domain;
re-timing, by the first circuit of the first clock domain, the digital input signal in accordance with the falling edge of the first clocking signal when the first clocking signal selection is lagging the second clocking signal;
re-timing, by the first circuit of the first clock domain, the digital input signal in accordance with the rising edge of the first clocking signal when the first clocking signal selection is leading the second clocking signal;
comparing, by a second circuit of the second clock domain, a third clocking signal associated with the re-timed digital input signal and a fourth clocking signal associated with the second clocking domain;
re-timing, by the second circuit of the second clock domain, the re-timed digital input signal in accordance with a rising edge of the fourth clocking signal when the fourth clocking signal selection is lagging the third clocking signal;
and
re-timing, by the second circuit of the second clock domain, the re-timed digital input signal in accordance with a falling edge of the fourth clocking signal when the fourth clocking signal selection is leading the third clocking signal.

4 more elements

Dependencies are inferred from the claim text.

Read-write data translation technique of asynchronous clock domains

Life of this patent

Read-write data translation technique of asynchronous clock domains

Life of this patent

Abstract

Claims20