Clock and data recovery circuit

A clock and data recovery circuit, comprising:

• a finite state machine (FSM) that comprises:
• a first accumulator configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle,
• a plurality of accumulators, wherein the first accumulator and the plurality of accumulators are connected in series, wherein each of the plurality of accumulators is configured to accumulate the input phase codes and lower order phase codes generated by a preceding accumulator for different FSM cycles and to generate a higher order phase code at each FSM cycle, and
• an end accumulator connected to a last accumulator in the plurality of accumulators, and configured to accumulate the input phase codes and phase codes generated by the last accumulator for different FSM cycles and to generate a final order phase code at each FSM cycle;
• and
• a phase interpolator configured to rotate a phase of the clock signal to provide a rotated clock based on the final order phase code.

A method for performing a clock and data recovery, comprising:

• generating an input phase code representing a phase timing difference between a data signal and a clock signal at each finite state machine (FSM) cycle;
• accumulating input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle;
• accumulating the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle;
• accumulating the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle;
• and
• rotating a phase of the clock signal to provide a rotated clock based on the third order phase code.