Back to results
US 2019/0058481 A1Published application
Digital Frequency-Division Phase-Locked Loop
AssigneeHuawei Technologies Co., Ltd.
InventorPeng Gao
Life of this patent
Estimating the term…
Abstract
A digital frequency-division phase-locked loop, including a time-to-digital converter (TDC), a digital loop filter (DLF), a digital-controlled oscillator (DCO), a feedback frequency divider (DIV), a sigma-delta modulator (SDM), and a calibration apparatus, where the calibration apparatus compensates for, based on a frequency control word and a frequency-division control word generated by the SDM, a digital signal output by the TDC to obtain a calibration signal. The DLF performs digital filtering on the calibration signal to obtain an oscillator frequency control signal and set the oscillator frequency control signal as an output signal of the DCO.
Claims20
A digital frequency-division phase-locked loop, comprising:
- a time-to-digital converter (TDC) configured to:
- receive a reference clock signal and a feedback clock signal;
- and
- identify a phase difference between the reference clock signal and the feedback clock signal to obtain a digital signal indicating the phase difference;
- a calibration apparatus coupled to the TDC and configured to:
- receive the digital signal, a frequency control word, and a frequency-division control word generated by a sigma-delta modulator (SDM) coupled to the calibration apparatus;
- and
- compensate for the digital signal based on the frequency control word and the frequency-division control word to obtain a calibration signal, the frequency control word indicating a nominal frequency-division value of the digital frequency-division phase-locked loop, the nominal frequency-division value being a ratio of a frequency of an oscillation signal to a frequency of the reference clock signal, the frequency-division control word indicating an actual frequency-division value of a feedback frequency divider (DIV) coupled to the TDC, and the actual frequency-division value being a ratio of the frequency of the oscillation signal to a frequency of the feedback clock signal;
- a digital loop filter (DLF) coupled to the calibration apparatus and configured to:
- receive the calibration signal;
- and
- perform digital filtering on the calibration signal to obtain an oscillator frequency control signal,
- the DIV being configured to perform frequency division on the oscillation signal to obtain the feedback clock signal,
- the SDM being configured to:
- receive the frequency control word;
- and
- generate the frequency-division control word based on the frequency control word;
- and
- a digital-controlled oscillator (DCO) coupled to the DLF and configured to:
- receive the oscillator frequency control signal;
- and
- generate the oscillation signal as an output signal of the digital frequency-division phase-locked loop under the control of the oscillator frequency control signal.
19 more elements
A chip, comprising:
- a plurality of logic gate circuits or transistor circuits;
- and
- a digital frequency-division phase-locked loop coupled to the logic gate circuits or the transistor circuits and comprising:
- a time-to-digital converter (TDC) configured to:
- receive a reference clock signal and a feedback clock signal;
- and
- identify a phase difference between the reference clock signal and the feedback clock signal to obtain a digital signal indicating the phase difference;
- a calibration apparatus coupled to the TDC and configured to:
- receive the digital signal, a frequency control word, and a frequency-division control word generated by a sigma-delta modulator (SDM) coupled to the calibration apparatus;
- and
- compensate for the digital signal based on the frequency control word and the frequency-division control word to obtain a calibration signal, the frequency control word indicating a nominal frequency-division value of the digital frequency-division phase-locked loop, the nominal frequency-division value being a ratio of a frequency of an oscillation signal to a frequency of the reference clock signal, the frequency-division control word indicating an actual frequency-division value of a feedback frequency divider (DIV) coupled to the TDC, and the actual frequency-division value being a ratio of the frequency of the oscillation signal to a frequency of the feedback clock signal;
- a digital loop filter (DLF) coupled to the calibration apparatus and configured to:
- receive the calibration signal;
- and
- perform digital filtering on the calibration signal to obtain an oscillator frequency control signal,
- the DIV being configured to perform frequency division on the oscillation signal to obtain the feedback clock signal,
- the SDM being configured to:
- receive the frequency control word;
- and
- generate the frequency-division control word based on the frequency control word;
- and
- a digital-controlled oscillator (DCO) coupled to the DLF and configured to:
- receive the oscillator frequency control signal;
- and
- generate the oscillation signal as an output signal of the digital frequency-division phase-locked loop under the control of the oscillator frequency control signal.
22 more elements
Dependencies are inferred from the claim text.