Injection-locked digital bang-bang phase-locked loop with timing calibration

A method of reducing jitter in a phase-locked loop, the method comprising:

• receiving a clock signal at a phase-locked loop and a downsampling circuit;
• based on a sign of the clock signal captured by a phase frequency detector included in the phase-locked loop, calibrating an injection signal timing and enabling output of the downsampling circuit;
• providing an injection signal to a digitally-controlled oscillator included in the phase-locked loop based at least in part on output of an injection pulser receiving an output of a digitally-controlled delay line, the digitally controlled delay line controlled by the calibrated injection signal timing to apply a variable delay to an output from the downsampling circuit;
• and
• outputting a clock signal from the digitally-controlled oscillator based at least in part on the output signal received from the injection pulser.

An injection-locked digital bang-bang phase-locked loop (PLL) circuit comprising:

• a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, the digital bang-bang PLL comprising:
• a bang-bang phase frequency detector;
• a digital loop filter connected to a signal output of the bang-bang phase frequency detector;
• a digitally controlled oscillator receiving an output signal of the digital loop filter, the digitally controlled oscillator configured to output a resulting clock signal at the output clock signal connection;
• and
• a divider providing a signal feedback from an output of the digitally controlled oscillator to the bang-bang phase frequency detector;
• a down-sampling circuit connected to the input clock signal connection;
• a digitally-controlled delay line receiving an output of the down-sampling circuit;
• an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to the digitally controlled oscillator;
• an injection timing calibration circuit connected to a control input of the digitally-controlled delay line;
• and
• a bandwidth optimization circuit connected to the signal output of the bang-bang phase frequency detector and having a control output connected to the digital loop filter.