Clock Buffer and Method Thereof

A method for improving noise immunity in a clock buffer circuit comprising:

• incorporating a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, a power pin, and a ground pin of the first inverter directly connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively, and wherein an output pin of the first inverter generates the second clock signal;
• incorporating a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, a power pin, and a ground pin of the second inverter directly connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively, and wherein an output pin of the second inverter generates the third clock signal;
• incorporating a first resistor to directly connect a first DC voltage to the first source node;
• and
• incorporating a second resistor to directly connect a second DC voltage to the second source node,
• wherein the first source node is connected to the first DC voltage only through the first resistor and the second source node is connected to the second DC voltage only through the second resistor, thereby configuring the circuit to have improved noise immunity.