Flip-flop with single pre-charge node
AssigneeSamsung Electronics Co., Ltd.
InventorsShyam AGARWAL, Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Kumar Ghosh, Parvinder Kumar Rana
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Abstract
Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.
Claims20
A flip-flop device, comprising:
- a master latch comprising at least one of a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors and a first plurality of N-type metal-oxide-semiconductor (NMOS) transistors;
- a slave latch comprising at least one of a second plurality of PMOS transistors and a second plurality of NMOS transistors;
- and
- an inverted clock signal input, wherein the inverted clock signal input is connected to the master latch and the slave latch;
- and
- wherein the master latch comprises a single pre-charge node.
A method for managing operation of a flip-flop device, the method comprising:
- connecting an inverted clock signal input to a master latch and a slave latch,
- the master latch comprising at least one of a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors and a first plurality of N-type metal-oxide-semiconductor (NMOS) transistors, and
- the slave latch comprising at least one of a second plurality of PMOS transistors and a second plurality of NMOS transistors;
- and
- wherein the master latch further comprises a single pre-charge node.
A flip-flop device, comprising:
- a master latch comprising at least one of a first plurality of P-type metal-oxide-semiconductor (PMOS) transistors and a first plurality of N-type metal-oxide-semiconductor (NMOS) transistors;
- a slave latch comprising at least one of a second plurality of PMOS transistors and a second plurality of NMOS transistors;
- and
- an clock signal input, wherein the clock signal input is connected to the master latch and the slave latch;
- and
- wherein the master latch comprises a single pre-charge node which is pre-charged to logic level high at every low level of a clock signal.
Dependencies are inferred from the claim text.