Increasing efficiency of a switched mode power converter
AssigneeTexas Instruments Incorporated
InventorsRobert Alan Neidorff, Joseph Maurice Khayat
Life of this patent
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Abstract
Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.
Claims18
An apparatus including:
- a first node to receive a control signal for a low side transistor of a power converter;
- a second node to receive a first delay control signal delayed from the control signal;
- a third node to receive a second delay control signal delayed from the first delay control signal;
- a low side driver node configured to couple to a gate of the low side transistor;
- a first circuit path, when enabled by the first delay control signal, configured to discharge the low side driver node from a first voltage to a second voltage below the first voltage;
- and
- a second circuit path, when enabled by the second delay control signal, configured to discharge the low side driver node from the second voltage to a third voltage below the second voltage.
An apparatus comprising:
- a first node to receive a control signal for a low side transistor of a power converter;
- a second node to receive a first delay control signal delayed from the control signal;
- a third node to receive a second delay control signal delayed from the first delay control signal;
- a low side driver node configured to couple to a gate of the low side transistor;
- an AND gate having a first input coupled to receive the control signal, a second input coupled to receive the second delay control signal, and a logic output;
- and
- an NMOS transistor coupled between the low side driver node and a ground terminal, the NMOS transistor having a gate coupled to the logic output.
-20. (canceled)
Dependencies are inferred from the claim text.