Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses
OwnerMarius Orlowski, Gargi Ghosh +1inventors
InventorsMarius Orlowski, Gargi Ghosh, Anshuman Verma
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Abstract
A vertical interconnect via having a first array of first metal interconnect wires extending along a first lateral direction made from a first material and a second array of second interconnect wires extending along a second lateral direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a metal-insulator-metal structure. The said metal-insulator-metal structure transforms to metal-metal-metal structure upon an application of electric pulse.
Claims18
1-7. (canceled)
A method of forming an electrical connection in the metallization backend of an assembled integrated circuit post manufacture of the integrated circuit comprising steps of:
- providing a first electrode made of a first material and adapted to function as a terminal;
- providing a second electrode made of a second material and adapted to function as a terminal;
- providing an insulator layer between said first and said second electrodes;
- and
- applying a voltage or current to one of said electrodes to create an active electrode while said other electrode is grounded, said voltage or current causes ions consisting of the material of the ungrounded electrode to form a conductor that electrically connects said electrodes.
A method of forming an electrical connection in the metallization backend of an assembled integrated circuit post manufacture of the integrated circuit comprising steps of:
- providing a first array of electrodes made of a first material and said electrodes adapted to function as one or more terminals;
- providing a second array of electrodes made of a second material and said electrodes adapted to function as one or more terminals;
- providing a dielectric layer between said arrays;
- arranging said arrays to form a plurality of intersections defined by said electrodes of said first array and said electrodes of said second array, wherein each intersection defines a two-terminal resistive memory cell;
- and
- applying a voltage or current to one of said electrodes to create an active electrode while said other electrode is grounded, said voltage or current causes one or more conductive paths to form in said dielectric that electrically connect said electrodes to form said memory cells.
A post fabrication method of forming an electrical connection in the metallization backend of an assembled integrated circuit comprising steps of:
- providing a first electrode made of a first material and adapted to function as a terminal;
- providing a second electrode made of a second material and adapted to function as a terminal;
- providing an insulator layer between said first and said second electrodes;
- and
- applying a voltage or current to one of said electrodes to create an active electrode while said other electrode is grounded, said voltage or current causes ions consisting of the material of the ungrounded electrode to form a conductor that electrically connects said electrodes.
Dependencies are inferred from the claim text.