Vertical transistors having improved gate length control

A method of forming a semiconductor device, the method comprising:

• forming a channel fin structure across from a major surface of a substrate, wherein a top surface of the channel fin structure extends in a fin-top-surface direction that is substantially horizontal with respect to the major surface of the substrate, wherein perimeter sidewalls extend around an outer circumference of the channel fin structure;
• forming a gate structure across from the major surface of the substrate and along ft the perimeter sidewalls of the channel fin structure, wherein a first top surface of the gate structure is above the top surface of the channel fin structure and extends in a first-top-surface direction that is substantially horizontal with respect to the major surface of the substrate;
• forming a protective dielectric over the first top surface of the gate structure;
• and
• defining a second top surface of the gate structure by selectively removing an exposed sidewall portion of the gate structure in a direction that is substantially horizontal with respect to the major surface of the substrate;
• wherein the first top surface of the gate structure and the second top surface of the gate structure are present in the gate structure at the same time;
• wherein a gate length dimension of the gate structure is defined by a gate-length distance from a bottom surface of the gate structure to the second top surface of the gate structure.