Transistor gate-channel arrangements
AssigneeIntel Corporation
InventorsGilbert W. Dewey, Rafael Rios, Shriram Shivaraman, Marko Radosavljevic, Kent E. Millard, Marc C. French, Van H. Le
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Abstract
Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.
Claims25
A transistor gate-channel arrangement, comprising:
- a channel material;
- and
- a transistor gate stack, including:
- a gate electrode material,
- a high-k dielectric material disposed between the gate electrode material and the channel material, and
- indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.
A transistor, comprising:
- a channel material;
- a gate electrode material;
- a multilayer gate oxide disposed between the gate electrode material and the channel material, wherein the multilayer gate oxide includes a high-k dielectric and indium gallium zinc oxide (IGZO), and the IGZO is in contact with the channel material;
- a source region;
- and
- a drain region.
A computing device, comprising:
- a substrate;
- and
- an integrated circuit (IC) die coupled to the substrate, wherein the IC die includes a transistor having:
- a channel material,
- a gate electrode material,
- a multilayer gate oxide disposed between the gate electrode material and the channel material, wherein the multilayer gate oxide includes a high-k dielectric and indium gallium zinc oxide (IGZO), and the IGZO is in contact with the channel material,
- a source region, and
- a drain region.
A method of manufacturing a transistor, comprising:
- providing a gate electrode material;
- providing a layer of high-k dielectric;
- and
- providing a layer of indium gallium zinc oxide (IGZO) such that the layer of high-k dielectric is disposed between the layer of IGZO and the gate electrode material.
Dependencies are inferred from the claim text.