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AssigneeIntel Corporation
InventorsHAN WUI THEN, SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, SANAZ K. GARDNER, SEUNG HOON SUNG
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Techniques are disclosed for forming transistors including retracted raised source/drain (S/D) to reduce parasitic capacitance. In some cases, the techniques include forming ledges for S/D epitaxial regrowth on a high-quality crystal nucleation surface. The techniques may also include forming the raised sections of the S/D regions (e.g., the portions adjacent to spacer material between the S/D regions and the gate material) in a manner such that the S/D raised sections are retracted from the gate material. This can be achieved by forming a notch at the interface between a polarization charge inducing layer and an oxide layer using a wet etch process, such that a relatively high-quality surface of the polarization charge inducing layer material is exposed for S/D regrowth. Therefore, the benefits derived from growing the S/D material from a high-quality nucleation surface can be retained while reducing the parasitic overlap capacitance penalty that would otherwise be present.
An integrated circuit including at least one transistor, the integrated circuit comprising:
An integrated circuit including at least one transistor, the integrated circuit comprising:
21-25. (canceled)
Dependencies are inferred from the claim text.