Memory circuit and formation method thereof

A memory circuit, comprising:

• a control device arranged within a substrate;
• a first memory device arranged within a dielectric structure over the substrate and having a first lower electrode separated from a first upper electrode by a first data storage layer;
• a plurality of interconnect layers surrounded by the dielectric structure and configured to couple the first upper electrode to the control device and the first lower electrode to a first bit-line;
• and
• a second memory device arranged within the dielectric structure and having a second lower electrode separated from a second upper electrode by a second data storage layer, wherein the plurality of interconnect layers are configured to couple the second upper electrode to a second bit-line and the second lower electrode to the control device.

A method of forming a memory circuit, comprising:

• forming a control device within a substrate;
• forming a first memory device having a first lower electrode coupled to a first bit-line and a first upper electrode coupled to the control device;
• and
• forming a second memory device having a second lower electrode coupled to the control device and a second upper electrode coupled to a second bit-line.