Semiconductor storage element, semiconductor device, electronic device, and manufacturing method of semiconductor storage element

A semiconductor device comprising:

• a storage device in which semiconductor storage elements are arranged in a matrix,
• wherein each of the semiconductor storage elements includes
• a first semiconductor layer of a first conductivity type,
• a second semiconductor layer of a second conductivity type that is provided below the first semiconductor layer,
• a gate electrode provided on the first semiconductor layer,
• a gate insulator film provided between the first semiconductor layer and the gate electrode,
• a drain region of the second conductivity type that is provided in the first semiconductor layer on one side of the gate electrode,
• a source region of the second conductivity type that is provided in the first semiconductor layer on another side facing the one side across the gate electrode, and
• a bit line configured to electrically connect with both of the source region and the first semiconductor layer.

A electronic device comprising:

• a storage device in which semiconductor storage elements are arranged in a matrix,
• wherein each of the semiconductor storage elements includes
• a first semiconductor layer of a first conductivity type,
• a second semiconductor layer of a second conductivity type that is provided below the first semiconductor layer,
• a gate electrode provided on the first semiconductor layer,
• a gate insulator film provided between the first semiconductor layer and the gate electrode,
• a drain region of the second conductivity type that is provided in the first semiconductor layer on one side of the gate electrode,
• a source region of the second conductivity type that is provided in the first semiconductor layer on another side facing the one side across the gate electrode, and
• a bit line configured to electrically connect with both of the source region and the first semiconductor layer.

A manufacturing method of a semiconductor storage element, the manufacturing method comprising:

• a process of forming a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type that is to be provided below the first semiconductor layer;
• a process of forming a gate insulator film on the first semiconductor layer;
• a process of forming a gate electrode on the gate insulator film;
• a process of forming a drain region of the second conductivity type, in the first semiconductor layer on one side of the gate electrode, and forming a source region of the second conductivity type, in the first semiconductor layer on another side facing the one side across the gate electrode;
• and
• a process of forming a bit line configured to electrically connect with both of the source region and the first semiconductor layer.