Fan-Out Wafer Level Package Structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJing-Cheng Lin
Life of this patent
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Abstract
A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- attaching a semiconductor die to a carrier;
- attaching a via die adjacent to the semiconductor die;
- applying a molding compound around the semiconductor die and the via die;
- planarizing the molding compound to expose through vias in the via die and expose the semiconductor die;
- forming a first redistribution layer in electrical connection with both the through vias and the semiconductor die;
- and
- connecting a semiconductor structure to the through vias, the semiconductor structure being located on an opposite side of the first semiconductor die than the first redistribution layer.
A method of manufacturing a semiconductor device, the method comprising:
- encapsulating a first semiconductor die and a via die with an encapsulant;
- performing a grinding process until a through via and the first semiconductor die are planar with each other, the through via being located within the via die;
- connecting the through via and the first semiconductor die to external connectors through a redistribution layer, the redistribution layer being located along a first side of the first semiconductor die;
- and
- connecting the through vias to a semiconductor structure, the semiconductor structure being located along a second side of the first semiconductor die opposite the first side.
A method of manufacturing a semiconductor device, the method comprising:
- providing an encapsulated substrate with a constant thickness, the encapsulated substrate comprising a first semiconductor die, a via, and an encapsulant;
- forming a first redistribution layer adjacent to a first side of the encapsulated substrate;
- attaching first external contacts directly to the first redistribution layer;
- and
- attaching a semiconductor structure to the via extending through the encapsulant, the semiconductor structure being adjacent to a second side of the encapsulated substrate, the second side being opposite the first side.
Dependencies are inferred from the claim text.