Package method for generating package structure with fan-out interfaces
AssigneePowertech Technology Inc.
InventorsHung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
Life of this patent
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Abstract
A semiconductor package structure includes an encapsulant, a chip module, at least one auxiliary conduction block, and a redistribution layer. The chip module is encapsulated by the encapsulant. The chip module has a chip. Each of the at least one auxiliary conduction block has a plurality of auxiliary conductive bumps and a mold layer encapsulating the plurality of auxiliary conductive bumps. The redistribution layer is disposed on the encapsulant. The redistribution layer is used to electrically connect the chip of the chip module and the at least one auxiliary conduction block.
Claims20
A semiconductor package structure, comprising:
- a chip module having a chip, the chip encapsulated by a first mold layer;
- at least one auxiliary conduction block, each of the at least one auxiliary conduction block having a plurality of auxiliary conductive pillars and a second mold layer encapsulating the plurality of auxiliary conductive pillars;
- an encapsulant encapsulating the first mold layer and the second mold layer;
- and
- a redistribution layer disposed on the encapsulant, the redistribution layer being configured to electrically connect the chip of the chip module and the at least one auxiliary conduction block,
- wherein the chip module, the at least one auxiliary conduction block, and the encapsulant are coplanar to each other.
(canceled)
A method of forming a semiconductor package, comprising:
- providing a tooling plate;
- disposing a chip module on the tooling plate, the chip module having a chip_encapsulated by a first mold layer;
- disposing at least one auxiliary conduction block on the tooling plate, each of the at least one auxiliary conduction block having a plurality of auxiliary conductive pillars and a second mold layer encapsulating the plurality of auxiliary conductive pillars;
- forming an encapsulant on the tooling plate to encapsulate the chip module and the at least one auxiliary conduction block;
- forming a redistribution layer on the tooling plate, the redistribution layer being configured to electrically connect the chip of the chip module and the at least one auxiliary conduction block;
- and
- removing the tooling plate
- wherein the chip module, the at least one auxiliary conduction block, and the encapsulant are coplanar to each other.
Dependencies are inferred from the claim text.