Wafer-level package with enhanced performance
AssigneeQorvo US, Inc.
InventorsJulio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, JR., Jon Chadwick
Life of this patent
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AssigneeQorvo US, Inc.
InventorsJulio C. Costa, Jan Edward Vandemeer, Jonathan Hale Hammond, Merrill Albert Hatcher, JR., Jon Chadwick
Estimating the term…
The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.
An apparatus comprising:
Dependencies are inferred from the claim text.