Semiconductor device including contact structure

A semiconductor device, comprising:

• a first fin active region and a second fin active region, disposed on a first device region of a semiconductor substrate and opposing each other;
• a groove portion disposed between the first fin active region and the second fin active region;
• a first gate structure on the first fin active region and a second gate structure on the second fin active region, each of the first gate structure and the second gate structure including gate spacers, as well as a gate electrode and a gate capping pattern, disposed between the gate spacers and stacked in sequence;
• an insulating structure disposed between the first gate structure and the second gate structure and extending into the groove portion, the insulating structure including a lower insulating pattern in the groove portion and an upper insulating pattern on the lower insulating pattern;
• a first contact structure disposed between the insulating structure and the first gate structure;
• and
• a second contact structure disposed between the insulating structure and the second gate structure,
• wherein upper surfaces of the first contact structure, the second contact structure, the upper insulating pattern, and the gate capping pattern are coplanar with each other.

A semiconductor device, comprising:

• an isolation region defining a lower active region and including silicon oxide;
• a first FinFET and a second FinFET, disposed on the lower active region and disposed adjacent to each other, the first FinFET including a first source/drain region and a first gate electrode, the second FinFET including a second source/drain region and a second gate electrode, and the first source/drain region being disposed adjacent to the second source/drain region;
• a first gate capping pattern and a second gate capping pattern, disposed on the first gate electrode and the second gate electrode, respectively;
• a first contact structure and a second contact structure, disposed on the first source/drain region and the second source/drain region, respectively;
• a lower insulating pattern disposed on the lower active region and disposed between the first source/drain region and the second source/drain region;
• and
• an upper insulating pattern disposed on the lower insulating pattern and disposed between the first contact structure and the second contact structure,
• wherein silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

A semiconductor device, comprising:

• a lower active region defined by an isolation region;
• a first fin active region and a second fin active region, disposed on the lower active region and having opposing ends;
• a first gate structure on the first fin active region and a second gate structure on the second fin active region, each of the first gate structure and the second gate structure including gate spacers, as well as a gate electrode and a gate capping pattern, disposed between the gate spacers and stacked in sequence;
• an interlayer insulating pattern disposed on the isolation region;
• an insulating structure disposed between the first fin active region and the second fin active region and disposed between the first gate structure and the second gate structure;
• and
• a first contact structure disposed between the insulating structure and the first gate structure and a second contact structure disposed between the insulating structure and the second gate structure,
• wherein the insulating structure includes a lower insulating pattern disposed in-between the first fin active region and the second fin active region, and an upper insulating pattern disposed on the lower insulating pattern and having a width different from a width of the lower insulating pattern, and
• wherein a material of the interlayer insulating pattern has etching selectivity with respect to an insulating material which the gate capping pattern and the upper insulating pattern are formed of.