Semiconductor device, method of manufacturing same, and power converter

A semiconductor device comprising:

• a semiconductor substrate;
• a semiconductor layer of a first conductivity type disposed on a first main surface of the semiconductor substrate;
• a first semiconductor region of a second conductivity type selectively provided in an upper layer portion of the semiconductor layer;
• a second semiconductor region of the first conductivity type selectively provided in an upper layer portion of the first semiconductor region;
• a gate insulation film provided in contact with surfaces of the first and second semiconductor regions and the semiconductor layer;
• an insulation film that is thicker than the gate insulation film and provided in a region of the semiconductor layer in which the gate insulation film is not provided;
• a gate electrode provided on at least the gate insulation film;
• an interlayer insulation film provided to cover the gate electrode;
• a contact hole formed through the gate insulation film and the interlayer insulation film and exposing at least the second semiconductor region at a bottom thereof;
• a first main electrode provided on the interlayer insulation film and electrically connected to the second semiconductor region via the contact hole;
• and
• a second main electrode disposed on a second main surface of the semiconductor substrate,
• wherein the first main electrode includes:
• an underlying electrode film connected to the second semiconductor region via the contact hole;
• and
• a copper film provided on the underlying electrode film, and
• the copper film has a thickness greater than or equal to 15 μm, and
• the copper film includes a stress relaxation layer having a smaller grain size than the other portion of the copper film, above a region that includes at least a junction between the gate insulation film and the insulation film.

A method of manufacturing a semiconductor device, comprising:

• (a) forming a semiconductor layer of a first conductivity type on a first main surface of a semiconductor substrate;
• (b) selectively forming a first semiconductor region of a second conductivity type in an upper layer portion of the semiconductor layer;
• (c) selectively forming a second semiconductor region of the first conductivity type in an upper layer portion of the first semiconductor region;
• (d) forming a gate insulation film in contact with surfaces of the first and second semiconductor regions and the semiconductor layer;
• (e) forming an insulation film thicker than the gate insulation film in a region of the semiconductor layer where the gate insulation film is not provided;
• (f) forming a gate electrode on at least the gate insulation film;
• (g) forming an interlayer insulation film to cover the gate electrode;
• (h) forming a contact hole through the gate insulation film and the interlayer insulation film, the contact hole exposing at least the second semiconductor region at a bottom thereof;
• (i) forming a first main electrode on the interlayer insulation film, the first main electrode being electrically connected to the second semiconductor region via the contact hole;
• and
• (j) forming a second main electrode on a second main surface of the semiconductor substrate,
• the forming (i) including:
• (i-1) forming an underlying electrode film that is connected to the second semiconductor region via the contact hole;
• (i-2) forming asperities on a surface of at least part of the underlying electrode film on a side opposite to the interlayer insulation film;
• and
• (i-3) forming a copper film on the underlying electrode film by electroplating.