Structure and method for testing three-dimensional memory device

A method for forming a memory device, comprising:

• forming a memory array structure comprising a memory array stack and one or more memory array contacts;
• forming a through array contact (TAC) extending vertically through at least part of the memory array stack of the memory array structure;
• forming a first dielectric layer at a front side of the memory array structure;
• forming a plurality of first contacts in the first dielectric layer;
• forming a plurality of conductive pads at a backside of the memory array structure;
• forming a complementary metal-oxide-semiconductor (CMOS) structure;
• forming a metal layer at a front side of the CMOS structure, the metal layer comprising a plurality of metal patterns;
• forming a second dielectric layer on the metal layer;
• forming a plurality of second contacts in the second dielectric layer;
• and
• joining the first dielectric layer and the second dielectric layer face to face, such that the memory array structure is above the CMOS structure, and one or more electrical connections are formed by at least the plurality of conductive pads, the TAC, the plurality of first contacts, the plurality of second contacts, the plurality of metal patterns in the metal layer, and at least one of the one or more memory array contacts.

A method for testing a three-dimensional (3D) memory device, comprising:

• applying an input signal to a first conductive pad of the memory device by a first probe of a probe card, wherein at least part of the first conductive pad is on a top surface of the memory device;
• transmitting, through at least the first conductive pad, a first through array contact (TAC) of the memory device, a first interconnect structure passing through a bonding interface of the memory device, and at least one of a memory array contact and a test circuit, the input signal to a test structure of the memory device;
• receiving, through at least a second interconnect structure passing through the bonding interface, a second TAC of the memory device, and the at least one of the memory array contact and the test circuit, an output signal from the test structure;
• measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card, wherein at least part of the second conductive pad is on the top surface of the memory device;
• and
• determining a characteristic of the test structure based on the input signal and the output signal.