Memory device and operating method thereof
AssigneeSK hynix Inc.
InventorsHee Youl LEE, Sung Ho BAE
Life of this patent
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Abstract
A memory device having an improved program speed may include a memory cell array including a plurality of memory cells, each being programmed to one of a plurality of program states; a peripheral circuit configured to perform a program operation to one or more of the plurality of memory cells, the program operation including a program voltage applying operation and a verify operation; and a control logic configured to control the peripheral circuit to simultaneously perform the verify operation for at least two program states by applying bit line voltages having different voltage levels to bit lines coupled to the plurality of memory cells.
Claims16
A memory device, comprising:
- a memory cell array including a plurality of memory cells, each being programmed to one of a plurality of program states;
- a peripheral circuit configured to perform a program operation to one or more of the plurality of memory cells, the program operation including a program voltage applying operation and a verify operation;
- and
- a control logic configured to control the peripheral circuit to simultaneously perform the verify operation for at least two program states by applying bit line voltages having different voltage levels to bit lines coupled to the plurality of memory cells.
A method of operating a memory device including a plurality of memory cells each being programmed to have one of a plurality of program states, the method comprising:
- applying a program voltage to a word line coupled to the plurality of memory cells;
- and
- simultaneously verifying at least two program states by applying bit line voltages different from each other to bit lines coupled to the plurality of memory cells.
A memory device, comprising:
- a memory cell array including a plurality of memory cells;
- a peripheral circuit configured to perform a program voltage applying operation and a program verify operation on selected memory cells coupled to a selected word line, among the plurality of memory cells;
- and
- a control logic configured to control the peripheral circuit to simultaneously perform the program verify operation of applying a verify voltage to the selected word line and applying bit line voltages determined based on a threshold voltage difference between target program states of the selected memory cells and a program state corresponding to the verify voltage to bit lines coupled to the selected memory cells.
Dependencies are inferred from the claim text.