Semiconductor storage device
AssigneeToshiba Memory Corporation
InventorHiromitsu KOMAI
Life of this patent
Estimating the term…
Abstract
A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.
Claims20
A semiconductor storage device comprising:
- a memory cell array that includes first to sixth memory cells;
- first to third bit lines that are respectively connected to the first to third memory cells and are disposed in sequence in a first direction;
- fourth to sixth bit lines that are respectively connected to the fourth to sixth memory cells and are disposed in sequence in the first direction;
- a sense amplifier that includes first to sixth sense circuits respectively connected to the first to sixth bit lines and in which the first and fourth sense circuits are arranged along a second direction crossing the first direction, the second and fifth sense circuits are arranged along the second direction, and the third and sixth sense circuits are arranged along the second direction;
- a data register that includes first to sixth latch circuits respectively connected to the first to sixth sense circuits and in which the first and fourth latch circuits are connected to the first and fourth sense circuits via a first bus, the second and fifth latch circuits are connected to the second and fifth sense circuits via a second bus, and the third and sixth latch circuits are connected to the third and sixth sense circuits via a third bus;
- and
- an input and output circuit that is connected to the first and fourth latch circuits via a first data line, is connected to the second and fifth latch circuits via a second data line, and is connected to the third and sixth latch circuits via a third data line.
A semiconductor storage device comprising:
- a plurality of memory cells;
- bit lines respectively connected to the memory cells;
- a sense amplifier that includes sense circuits respectively connected to the bit lines;
- a data register that includes latch circuits respectively connected to the sense circuits;
- an input and output circuit that is connected to a first set of latch circuits via a first data line, a seconds set of latch circuits via a second data line, and a third set of latch circuits via a third data line;
- and
- a control circuit configured to perform a first read operation to read data from the memory cell array to the data register in response to a first command, and perform a second read operation to output the data from the data register through the input output circuit in response to a second command that is received following the first command but prior to completion of the first read operation.
A method of performing a read operation in a semiconductor storage device including a plurality of memory cells, bit lines respectively connected to the memory cells, a sense amplifier that includes sense circuits respectively connected to the bit lines, a data register that includes latch circuits respectively connected to the sense circuits, and an input and output circuit that is connected to a first set of latch circuits via a first data line, a seconds set of latch circuits via a second data line, and a third set of latch circuits via a third data line, said method comprising:
- in response to a first command, performing a first read operation to read data from the memory cell array to the data register;
- and
- in response to a second command that is received following the first command but prior to completion of the first read operation, performing a second read operation to output the data from the data register through the input output circuit.
Dependencies are inferred from the claim text.