Provision of structural integrity in memory device
AssigneeIntel Corporation
InventorMichael J. BERNHARDT
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of wordlines disposed in a memory region of a die, and a first fill layer deposited between adjacent wordlines of the plurality of wordlines in the memory region, to provide structural integrity for the memory array. At least a portion of a periphery region of the die adjacent to the memory region may be substantially filled with a second fill layer that is different than the first fill layer. Other embodiments may be described and/or claimed.
Claims25
-25. (canceled)
An apparatus, comprising:
- a memory region that includes a plurality of wordlines disposed adjacent each other, the wordlines having first sides and second sides opposite the first sides, wherein the first sides of the wordlines define a plane in a die;
- a periphery region disposed adjacent to the memory region, wherein the periphery region includes a first side and a second side opposite the first side, wherein the first side of the periphery region further defines the plane of the die;
- and
- a fill layer deposited in the periphery region to substantially fill at least a portion of the periphery region, wherein the fill layer covers the first side of the at least a portion of the periphery region, wherein the fill layer comprises inorganic dielectric material.
An apparatus, comprising:
- a memory region that includes a plurality of wordlines disposed adjacent each other, the wordlines having first sides and second sides opposite the first sides, wherein the first sides of the wordlines define a plane in a die;
- a periphery region disposed adjacent to the memory region, wherein the periphery region includes a first side and a second side opposite the first side, wherein the first side of the periphery region further defines the plane of the die;
- and
- a fill layer deposited in the periphery region to substantially fill the periphery region, wherein the fill layer covers the first side of the periphery region, wherein the fill layer comprises alkoxide compound material.
An apparatus, comprising:
- a processor;
- and
- a memory coupled with the processor, wherein the memory includes:
- a memory region that includes a plurality of wordlines disposed adjacent each other, the wordlines having first sides and second sides opposite the first sides, wherein the first sides of the wordlines define a plane in a die;
- a periphery region disposed adjacent to the memory region, wherein the periphery region includes a first side and a second side opposite the first side, wherein the first side of the periphery region further defines the plane of the die;
- and
- a fill layer deposited in the periphery region to substantially fill at least a portion of the periphery region, wherein the fill layer covers the first side of the at least a portion of the periphery region, wherein the fill layer comprises inorganic dielectric material or alkoxide compound material.
A method, comprising:
- forming a memory region in a die, including disposing a plurality of wordlines adjacent each other, the wordlines having first sides and second sides opposite the first sides, wherein the first sides of the wordlines define a plane in a die;
- forming a periphery region adjacent to the memory region of the die, wherein the periphery region includes a first side and a second side opposite the first side, wherein the first side of the periphery region further defines the plane of the die;
- and
- depositing a fill layer in the periphery region to substantially fill at least a portion of the periphery region, and to cover the first side of the at least a portion of the periphery region, wherein the fill layer comprises inorganic dielectric material.
Dependencies are inferred from the claim text.