Self-Timing Path with Substrate-Connected Dummy Bitline
AssigneeArm Limited
InventorsAbhishek B. Akkur, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Satinderjit Singh, Vasimraja Bhavikatti
Life of this patent
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Abstract
A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.
Claims16
A circuit comprising:
- a substrate;
- a dummy wordline;
- a dummy bitline;
- a pMOSFET having a date terminal coupled to the dummy wordline, a source terminal coupled to a supply rail, and a drain terminal connected to the dummy bitline;
- at least one dummy cell of a first type, each dummy cell of the first type comprising:
- an active pulldown nMOSFET having a gate terminal, a source terminal, and a drain terminal;
- and
- a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and
- a drain terminal connected to the dummy bitline;
- and
- a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to the substrate.
(canceled)
15-19. (canceled)
A circuit comprising:
- a substrate;
- a bitcell array including bitlines and wordlines;
- a dummy bitline to track the bitlines of the bitcell array;
- a dummy wordline to track the wordlines of the bitcell array;
- a pass nMOSFET having a gate terminal connected to the dummy wordline, a drain terminal connected to the dummy bitline, and a source terminal;
- an active pulldown nMOSFET comprising a gate terminal, a source terminal, and a drain terminal coupled to the source terminal of the pass nMOSFET;
- a supply rail coupled to the gate terminal of the active pulldown nMOSFET;
- a substrate-connected dummy bitline to track the bitlines of the bitcell array, wherein the substrate-connected dummy bitline is coupled to the source terminal of the active pulldown nMOSFET;
- and
- a pMOSFET having a gate terminal coupled to the dummy wordline, a source terminal coupled to the supply rail, and a drain terminal connected to the dummy bitline.
Dependencies are inferred from the claim text.