Memory device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorTatsuya ONUKI
Life of this patent
Estimating the term…
Abstract
A memory device with reduced power consumption is provided. The memory device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of supplying precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. The latch circuit in a standby state is preferably supplied with the precharge voltage and one of low power supply voltage and high power supply voltage.
Claims14
A memory device comprising:
- a plurality of memory cells;
- a precharge circuit;
- a latch circuit electrically connected to a first wiring and a second wiring;
- a bit line pair comprising a first bit line and a second bit line;
- a local bit line pair comprising a first local bit line and a second local bit line;
- a third transistor between the first bit line and the first local bit line;
- and
- a fourth transistor between the second bit line and the second local bit line,
- wherein each of the plurality of memory cells comprises a first transistor between the first local bit line and a first capacitor, and a second transistor between the second local bit line and a second capacitor,
- wherein the precharge circuit is configured to supply a precharge voltage to the local bit line pair, and
- wherein when the first transistor, the second transistor, the third transistor, and the fourth transistor are off, one of the first wiring and the second wiring is configured to supply the precharge voltage, and the other of the first wiring and the second wiring is configured to supply a power supply voltage.
4-8. (canceled)
A memory device comprising:
- a memory cell comprising a first transistor, a first capacitor, a second transistor, and a second capacitor;
- and
- a latch circuit electrically connected to a first local bit line, a second local bit line, a first wiring, and a second wiring,
- wherein one of a source and a drain of the first transistor is electrically connected to the first local bit line,
- wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor,
- wherein one of a source and a drain of the second transistor is electrically connected to the second local bit line,
- wherein the other of the source and the drain of the second transistor is electrically connected to the second capacitor, and
- wherein when the first transistor and the second transistor are off, one of the first wiring and the second wiring is configured to supply a precharge voltage, and the other of the first wiring and the second wiring is configured to supply a power supply voltage.
Dependencies are inferred from the claim text.