Power supply wiring in a semiconductor memory device
AssigneeMicron Technology, Inc.
InventorMamoru Nishizaki
Life of this patent
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Abstract
The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.
Claims12
1-9. (canceled)
A semiconductor device, comprising:
- an uppermost metal layer including a power supply enhancing wiring;
- power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer;
- at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer;
- and
- a memory bank, including:
- a plurality of sense amplifiers;
- a plurality of memory mats coupled to the sense amplifiers, the memory mats including first and second edge mats;
- and
- a global input/output line coupled to the sense amplifiers and disposed over the first edge mat and not disposed over the second edge mat;
- wherein the at least one memory device component disposed in vertical alignment with the via includes the second edge mat.
(canceled)
A semiconductor device, comprising:
- an uppermost metal layer including a power supply enhancing wiring;
- power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer;
- at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer;
- a plurality of memory mats;
- and
- a plurality of sense amplifiers arranged between at least some of the memory mats;
- wherein
- the plurality of memory mats include first and second memory mats that are directly adjacent such that no sense amplifier of the plurality of sense amplifiers is disposed between the first and second memory mats;
- and
- the at least one memory device component disposed in vertical alignment with the via includes the first memory mat.
Dependencies are inferred from the claim text.