Shift register, method for driving the same, and gate driving circuit
AssigneesBoe Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
InventorsMiao Zhang, Jing Sun, Wuxia Fu, Songmei Sun, Fangqing Li, Huanyu Li
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Abstract
The embodiments of the present disclosure provide a shift register, a method for driving the same, and a gate driving circuit. A pull-down sub-circuit of the shift register is under the control of a third clock signal terminal and a fourth clock signal terminal, wherein signals of the third clock signal terminal and the fourth clock signal terminal are mutually inverted signals, and signal periods of the third clock signal terminal and the fourth clock signal terminal are a half of a signal period of a first clock signal terminal or a second clock signal terminal.
Claims20
A shift register comprising an input sub-circuit, a reset sub-circuit, a control sub-circuit, a pull-down sub-circuit, and an output sub-circuit, wherein:
- the input sub-circuit is electrically connected to a signal input terminal and a pull-up node, and is configured to provide a signal of the signal input terminal to the pull-up node under control of the signal input terminal;
- the output sub-circuit is electrically connected to a first clock signal terminal, the pull-up node and a signal output terminal, and is configured to provide a signal of the first clock signal terminal to the signal output terminal under control of the pull-up node;
- the reset sub-circuit is electrically connected to a reset terminal, a power supply terminal, the signal output terminal, and the pull-up node, and is configured to provide a signal of the power supply terminal to the pull-up node and the signal output terminal under control of the reset terminal;
- the control sub-circuit is electrically connected to a second clock signal terminal and a pull-down node, and is configured to provide a signal of the second clock signal terminal to the pull-down node under control of the second clock signal terminal;
- and
- the pull-down sub-circuit is electrically connected to the pull-up node, the pull-down node, the power supply terminal, a third clock signal terminal, a fourth clock signal terminal, and the signal output terminal, and is configured to provide the signal of the power supply terminal to the pull-up node and the signal output terminal under control of the third clock signal terminal, the fourth clock signal terminal and the pull-down node;
- wherein, signals of the third clock signal terminal and the fourth clock signal terminal are mutually inverted signals, and signal periods of the third clock signal terminal and the fourth clock signal terminal are a half of a signal period of the first clock signal terminal or the second clock signal terminal.
Dependencies are inferred from the claim text.