Data transfer device, image processing device, and imaging device

An image processing device, comprising:

• a data transfer device which includes
• a DMA buffer section including a plurality of storage regions and configured to store data acquired by a DMA transfer in the storage regions in units of the DMA transfers;
• a buffer control section configured to output a first writing permission signal for permitting the DMA transfer for acquiring the data on the basis of presence or absence of a free storage region which is one of the storage regions where the data is not stored;
• a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer for acquiring the data within a predetermined period;
• a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal, and cause the data acquired by each of the DMA transfer to be sequentially stored in the free storage region;
• and
• a buffer reading control section configured to sequentially read the data stored in the storage region for each storage region,
• wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.

An imaging device, comprising:

• an image processing device which includes
• a data transfer device including
• a DMA buffer section including a plurality of storage regions and configured to store data acquired by a DMA transfer in the storage regions in units of the DMA transfers;
• a buffer control section configured to output a first writing permission signal for permitting the DMA transfer for acquiring the data on the basis of presence or absence of a free storage region which is one of the storage regions where the data is not stored;
• a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer for acquiring the data within a predetermined period;
• a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal, and cause the data acquired by each of the DMA transfer to be sequentially stored in the free storage region;
• and
• a buffer reading control section configured to sequentially read the data stored in the storage region for each storage region,
• wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.