Semiconductor device

The semiconductor device according to claim 22, wherein the master comprises first and second masters configured to issue requests to a memory;

• wherein the buffer is configured to store the requests issued from the first and the second masters, and configured to access the memory in accordance with the requests stored in the buffer;
• wherein the request issuing controller comprises:
• a first request issuing controller coupled between the first master and the memory controller;
• and
• a second request issuing controller coupled between the second master and the memory controller;
• wherein the central bus controller is configured to respectively grant access rights to the first and the second request issuing controllers based on space information of the buffer,
• wherein the first request issuing controller controls output of the request issued from the first master to the memory controller based on the access right granted from the central bus controller, and
• wherein the second request issuing controller controls output of the request issued from the second master to the memory controller based on the access right granted from the central bus controller.

A semiconductor device, comprising:

• a master that issues a request to a memory;
• a memory controller comprising a buffer that:
• stores the request;
• and
• accesses the memory in accordance with the stored request;
• a central bus controller that grants an access right based on space information of the buffer;
• and
• a request issuing controller that controls output of the request from the master to the memory controller based on the access right.

A semiconductor device, comprising:

• first and second masters for issuing requests to a memory;
• a memory controller including a buffer for storing the requests issued from the first and the second masters, and accessing the memory in accordance with the requests stored in the buffer;
• a first request issuing controller formed between the first master and the memory controller;
• a second request issuing controller formed between the second master and the memory controller;
• and
• a central bus controller for respectively granting access rights to the first and the second request issuing controllers based on space information of the buffer,
• wherein the first and second request issuing controllers control output of the requests issued from the first and second masters based on the access rights granted from the central bus controller.

A central bus controller for a semiconductor device, the central bus controller comprising:

• a Quality of Service (QoS) information register that stores QoS information of a plurality of masters;
• a right grant number controller that calculates a number of grantable access rights based on space information of a buffer of a memory controller that controls a memory;
• and
• a right grant selection controller that selects a master of the plurality of masters that will be granted an access right based on the QoS information and the number of grantable rights.