Method and apparatus for page table management
AssigneeIntel Corporation
InventorYEN HSIANG CHEW
Life of this patent
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Abstract
An apparatus and method for page table management. For example, one embodiment of an apparatus comprises: a memory management circuit to perform address translations using a page directory, a base page directory address identifying a location of the page directory in a system memory; a cache to reserve a first cache line containing the base page directory address stored in a modified state; cache snoop circuitry to detect a read to the base page directory address by a processor or graphics processing unit (GPU); and locking circuitry to assert a lock signal to change the state of the first cache line to a locked state, the memory management circuit to refrain from performing a page table walk until the lock signal is de-asserted.
Claims27
An apparatus comprising:
- a memory management circuit to perform address translations using a page directory, a base page directory address identifying a location of the page directory in a system memory;
- a cache to reserve a first cache line containing the base page directory address stored in a modified state;
- cache snoop circuitry to detect a read to the base page directory address by a processor or graphics processing unit (GPU);
- and
- locking circuitry to assert a lock signal to change the state of the first cache line to a locked state, the memory management circuit to refrain from performing a page table walk until the lock signal is de-asserted.
A method comprising:
- performing address translations using a page directory, a base page directory address identifying a location of the page directory in a system memory;
- reserving a first cache line containing the base page directory address stored in a modified state;
- detecting a read to the base page directory address by a processor or graphics processing unit (GPU);
- and
- asserting a lock signal to change the state of the first cache line to a locked state, the memory management circuit to refrain from performing a page table walk until the lock signal is de-asserted.
A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
- performing address translations using a page directory, a base page directory address identifying a location of the page directory in a system memory;
- reserving a first cache line containing the base page directory address stored in a modified state;
- detecting a read to the base page directory address by a processor or graphics processing unit (GPU);
- and
- asserting a lock signal to change the state of the first cache line to a locked state, the memory management circuit to refrain from performing a page table walk until the lock signal is de-asserted.
Dependencies are inferred from the claim text.